The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 22, 2007

Filed:

Dec. 16, 2003
Applicants:

Bruno W. Garlepp, Austin, TX (US);

Richard M. Barth, Ashland, OR (US);

Kevin S. Donnelly, Los Altos, CA (US);

Ely K. Tsern, Los Altos, CA (US);

Craig E. Hampel, San Jose, CA (US);

Jeffrey D. Mitchell, Santa Clara, CA (US);

James A. Gasbarro, Fox Chapel, PA (US);

Billy W. Garrett, Jr., Mountain View, CA (US);

Fredrick A. Ware, Los Altos Hills, CA (US);

Donald V. Perino, North Potomac, MD (US);

Inventors:

Bruno W. Garlepp, Austin, TX (US);

Richard M. Barth, Ashland, OR (US);

Kevin S. Donnelly, Los Altos, CA (US);

Ely K. Tsern, Los Altos, CA (US);

Craig E. Hampel, San Jose, CA (US);

Jeffrey D. Mitchell, Santa Clara, CA (US);

James A. Gasbarro, Fox Chapel, PA (US);

Billy W. Garrett, Jr., Mountain View, CA (US);

Fredrick A. Ware, Los Altos Hills, CA (US);

Donald V. Perino, North Potomac, MD (US);

Assignee:

Rambus, Inc., Los Altos, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 13/14 (2006.01);
U.S. Cl.
CPC ...
Abstract

A bus system for use with addressable memory has a global bus of bidirectional signal lines. The global bus has a first end and a second end. A master device transmits data to and receives data from the global bus at the first end. A global bus terminator is coupled to the global bus at the second end. One or more slave devices, including a last slave device at a furthest distance from the master device, each includes an active terminator coupled to at least some of the bidirectional signal lines of the global bus. The active terminator of only the last slave device is enabled.


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