The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 22, 2007

Filed:

May. 18, 2004
Applicant:

I-cheng Lin, Taipei, TW;

Inventor:

I-Cheng Lin, Taipei, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H02H 9/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

An integrated circuit preventing latchup. In the integrated circuit, an internal circuit is disposed in a substrate and has a parasitic SCR structure. At least one ESD protection circuit and active area are disposed on the substrate and coupled to a pad. A first current shunting diode has an anode coupled to the pad and a cathode coupled to a first voltage source. A second current shunting diode has a cathode coupled to the pad and an anode coupled to a second voltage source. Minority-carriers guard rings surround the first current shunting diode and the second shunting diode. Distance between the first and second current shunting diodes and the internal circuit, the active area and the ESD protection circuit exceed 80 μm.


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