The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 15, 2007
Filed:
Dec. 16, 2003
Jeffrey B. Reed, Austin, TX (US);
James S. Blomgren, Austin, TX (US);
Donald W. Glowka, Austin, TX (US);
Timothy A. Olson, Austin, TX (US);
Thomas W. Rudwick, Austin, TX (US);
Jeffrey B. Reed, Austin, TX (US);
James S. Blomgren, Austin, TX (US);
Donald W. Glowka, Austin, TX (US);
Timothy A. Olson, Austin, TX (US);
Thomas W. Rudwick, Austin, TX (US);
Intrinsity, Inc., Austin, TX (US);
Abstract
The matching algorithm of the layout synthesis method and apparatus disclosed locates transistor pattern matches in a design, links a parameterized tile to each identified match, and adjusts certain variable parameters of the linked parameterized tile to meet the physical design requirements of each located match. Each transistor pattern corresponds to a parameterized tile, which is an actual physical representation of the corresponding pattern and includes variable parameters, which may include transistor size. The matching algorithm locates matches in the design for an ordered list of patterns, names each located match, links the proper parameterized tile to each named match, and adjusts the tile's variable parameters as required. Transistors in the design are included in one and only one named located match.