Various methods and apparatuses to route multiple power rails to a cell

Abstract

Various methods and apparatuses are described in which an integrated circuit is organized into rows and columns of macro cells having a layout architecture that includes at least two metal layers and a plurality of traces carrying three or more different potentials of voltage routed by the metal layers. A first, a second, and a third adjacent metal layers extend across the integrated circuit. The first metal layer may be located between the second metal layer and the layer of the macro cells. The second metal layer may be located between the third metal layer and the first metal layer. The third metal layer may be orientated orthogonal to the second metal layer. The plurality of traces carry three or more different potentials of voltage and are routed in the metal layers. A first power trace supplies a VDD voltage potential. A second power trace supplies a VSS voltage potential. A third power trace supplies a third voltage potential. All three power supply traces connect to one or more transistors in a first macro cell.