The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 15, 2007

Filed:

Aug. 19, 2002
Applicants:

Leonard Forbes, Corvallis, OR (US);

Wendell P. Noble, Milton, VT (US);

Alan R. Reinberg, Westport, CT (US);

Inventors:

Leonard Forbes, Corvallis, OR (US);

Wendell P. Noble, Milton, VT (US);

Alan R. Reinberg, Westport, CT (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 21/8238 (2006.01); H01L 21/336 (2006.01); H01L 21/8236 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for forming NMOS and PMOS transistors that includes cutting a substrate along a higher order orientation and fabricating deep sub-micron NMOS and PMOS transistors on the vertical surfaces thereof. The complementary NMOS and PMOS transistors form a CMOS transistor pair. The transistors are preferably used in structures such as memory circuits, e.g., DRAMs, which are, in turn, used in a processor-based system. Ideally, the deep sub-micron NMOS and PMOS transistors are operated in velocity saturation for optimal switching operation.


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