The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7211902 B1

PDF
Full Text
Expired
Date of Patent:
May. 01, 2007

Filed:

Feb. 15, 2006
Applicant:

Takahisa Yamaha, Shizuoka, JP;

Inventor:

Takahisa Yamaha, Shizuoka, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/42 (2006.01); H01L 29/40 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor device having a semiconductor substrate and a bonding pad portion formed on the semiconductor substrate, the bonding pad portion having: an insulating film formed on the semiconductor substrate and a first-level conductive pad layer of a large island shape formed on the insulating film; first-level to (n−1)-level (n is an integer of 3 or larger) interlayer insulating films formed on and over the insulating film; second-level to n-level conductive pad layers formed on the interlayer insulating films in areas generally corresponding to an area where the first conductive pad layer was formed; a plurality of small diameter first through holes from the first-level to (n−1) level formed through the first-level to (n−1) level interlayer insulating films in areas generally corresponding to an area where the first conductive pad layer; a plurality of first contact plugs filled in the small diameter first through holes from the first-level to (n−1)-level, the first contact plugs at each level being conductive and electrically connecting two conductive pad layers adjacent along a normal to a surface of the semiconductor substrate, among the first-level to n-level conductive pad layers disposed in and on the first-level to (n−1)-level interlayer insulating films; an n-level interlayer insulating film formed on the (n−1)-level interlayer insulating film and covering the n-level conductive pad; a large diameter through hole formed though the n-level interlayer insulating film in an area corresponding to an area where the n-level conductive pad was formed; the large diameter through hole having a size corresponding to the n-level conductive pad to expose a substantial upper surface of the n-level conductive pad; and a bonding pad formed on the n-level interlayer insulating film and n-level conductive pad via the large diameter through hole.


Find Patent Forward Citations

Yamaha, Takahisa. (2007). Method of forming a bonding pad structure (U.S. Patent No. 7211902). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7211902

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