The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 24, 2007

Filed:

Jun. 19, 2003
Applicants:

Bruce Euzent, Sunnyvale, CA (US);

Roy Wei-guang Wu, San Jose, CA (US);

Jeffrey Barton, Santa Rosa, CA (US);

Anil Pannikkat, Santa Clara, CA (US);

Vadali Mahadev, San Jose, CA (US);

Tomas Jonsson, Santa Clara, CA (US);

Inventors:

Bruce Euzent, Sunnyvale, CA (US);

Roy Wei-Guang Wu, San Jose, CA (US);

Jeffrey Barton, Santa Rosa, CA (US);

Anil Pannikkat, Santa Clara, CA (US);

Vadali Mahadev, San Jose, CA (US);

Tomas Jonsson, Santa Clara, CA (US);

Assignee:

Altera Corporation, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01);
U.S. Cl.
CPC ...
Abstract

An apparatus performs reliability assessment of electronic hardware. The apparatus includes a test assembly. The test assembly includes at least one programmable logic device (PLD). The PLD is configured to provide a logic function, such as the function of a plurality of inverters coupled in a cascade manner. The apparatus further includes a signal source coupled to the test assembly. The signal source provides a stimulus signal to the test assembly. The apparatus also includes a signal monitor coupled to the test assembly. The signal monitor monitors a response signal generated by the test assembly.


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