The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 24, 2007

Filed:

Oct. 31, 2001
Applicants:

Sandeep Khanna, Santa Clara, CA (US);

Jose Pio Pereira, Santa Clara, CA (US);

Sunder Raj Rathnavelu, Marlboro, NJ (US);

Ronald S. Jankov, Woodside, CA (US);

Inventors:

Sandeep Khanna, Santa Clara, CA (US);

Jose Pio Pereira, Santa Clara, CA (US);

Sunder Raj Rathnavelu, Marlboro, NJ (US);

Ronald S. Jankov, Woodside, CA (US);

Assignee:

Netlogic Microsystems, Inc., Mountain View, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

An apparatus and method for generating a comparand in a content addressable memory array. For one embodiment, the apparatus includes a content addressable memory (CAM) array and translation circuitry. The CAM array receives a comparand and the translation circuitry includes at least one first input, at least one second input, and at least one output. The first input is configured to receive an input data having a plurality of bit groups, wherein a first bit group has a first position in the input data relative to other bit groups. The second input is configured to receive translation information indicative of translation of the first bit group from the first position to a different position in a comparand. The output is coupled to the CAM array to transmit the comparand to the CAM array. For one example, the translation circuitry includes a switch circuit that may include one or more multiplexers or demultiplexers. The translation circuitry may also include one or more storage elements to store the translation information, and one or more decode circuitry to decode the translation information and establish switch circuit connections between the first position and the position in the comparand.


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