The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 24, 2007

Filed:

May. 24, 2005
Applicants:

Damian A. Carver, Colorado Springs, CO (US);

Muhammad I. Chaudhry, Colorado Springs, CO (US);

Inventors:

Damian A. Carver, Colorado Springs, CO (US);

Muhammad I. Chaudhry, Colorado Springs, CO (US);

Assignee:

Atmel Corporation, San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/788 (2006.01); H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
Abstract

An EEPROM memory transistor having a floating gate. The floating gate is formed using a BiCMOS process and has a first sinker dopant region proximate to a tunnel diode window, and a second sinker dopant region proximate to a coupling capacitor region. An optional third sinker region may be formed proximate to a source junction of the EEPROM memory transistor. Also, a shallow trench isolation (STI) region may be formed between the first and second sinker dopant regions.


Find Patent Forward Citations

Carver, Damian. (2007). Low-cost, low-voltage single-layer polycrystalline eeprom memory cell integration into bicmos technology (U.S. Patent No. 7208795). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7208795

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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