Semiconductor chip, chip stack package and manufacturing method

Abstract

A semiconductor chip with conductive wiring that is routed to the edge of the substrate from the chip's backside. A plurality of such semiconductor chips are stacked and electrically connected using a wiring element that is a circuit board or conductive adhesive strips. The wiring element connects the conductive wiring of each semiconductor chip along the sides of the chips to the package substrate. A method of manufacturing the semiconductor chip includes batch manufacturing a plurality of die on a wafer with an active surface on which a plurality bonding pads are formed, and a backside which is the rear side of the active surface; forming a circuit groove on the backside; applying conductive wiring on the circuit groove using a conductive material; and separating the wafer into a plurality of semiconductor chips. A method of manufacturing the chip stack package with a plurality of such semiconductor chips having bump pads and connection pads routed to the side surface of the semiconductor chip includes stacking and bonding the bonding pad of the upper semiconductor chip on the bump pad of a lower semiconductor chip; electrically connecting the bonding pad of the lowest semiconductor chip to the substrate by bump bonding electrically connecting the wiring element to the connection pad of the semiconductor chip and the substrate; and connecting an external connection to the substrate.