The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 17, 2007

Filed:

Mar. 26, 2003
Applicants:

Hiroto Yoshioka, Tenri, JP;

Tatsuya Fujita, Soraku-gun, JP;

Hisao Ochi, Tenri, JP;

Toshinori Sugihara, Tenri, JP;

Takeshi Hara, Ikoma-gun, JP;

Masashi Kawasaki, Sendai-shi Miyagi, JP;

Hideo Ohno, Sendai-shi Miyagi, JP;

Inventors:

Hiroto Yoshioka, Tenri, JP;

Tatsuya Fujita, Soraku-gun, JP;

Hisao Ochi, Tenri, JP;

Toshinori Sugihara, Tenri, JP;

Takeshi Hara, Ikoma-gun, JP;

Masashi Kawasaki, Sendai-shi Miyagi, JP;

Hideo Ohno, Sendai-shi Miyagi, JP;

Assignees:

Other;

Sharp Kabushiki Kaisha, Osaka, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/58 (2006.01);
U.S. Cl.
CPC ...
Abstract

In an inverse-stagger MOSFET (), a gate insulating layer () made of amorphous aluminum oxide is so formed as to face a channel layer () which serves as the semiconductor layer, and which is made of zinc oxide. With this arrangement, a defect level at an interface between the channel layer () and the gate insulating layer () is reduced, thereby obtaining performance equivalent to that of a semiconductor apparatus in which all the layered films are crystalline. This technique is applicable to a staggered MOSFET and the like, and has high versatility.


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