The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 17, 2007
Filed:
Jun. 24, 2004
Yong-sun Lee, Seoul, KR;
Jae-min Yu, Seoul, KR;
Don-woo Lee, Hwaseong-si, KR;
Jung-hun Cho, Gunpo-si, KR;
Chul-soon Kwon, Seoul, KR;
Jung-ho Moon, Yongin-si, KR;
In-gu Yoon, Suwon-si, KR;
Jae-hyun Park, Yongin-si, KR;
Yong-Sun Lee, Seoul, KR;
Jae-Min Yu, Seoul, KR;
Don-Woo Lee, Hwaseong-si, KR;
Jung-Hun Cho, Gunpo-si, KR;
Chul-Soon Kwon, Seoul, KR;
Jung-Ho Moon, Yongin-si, KR;
In-Gu Yoon, Suwon-si, KR;
Jae-Hyun Park, Yongin-si, KR;
Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;
Abstract
A method of fabricating a flash memory cell having a split gate structure. A sacrificial layer is formed on a floating gate layer formed on a semiconductor substrate. The sacrificial layer is etched to form an opening exposing a portion of the floating gate layer. A gate interlayer insulating layer pattern is formed inside the opening. After removing the sacrificial layer pattern and etching the floating gate layer (using the gate interlayer insulating layer pattern as an etch mask), a floating gate is formed under the gate interlayer insulating layer pattern. A control gate is formed overlapping a portion of the floating gate.