The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 10, 2007

Filed:

May. 23, 2005
Applicants:

Robert J. Proebsting, Senora, CA (US);

Cesar A. Talledo, Sunnyvale, CA (US);

David J. Pilling, Los Altos Hills, CA (US);

Inventors:

Robert J. Proebsting, Senora, CA (US);

Cesar A. Talledo, Sunnyvale, CA (US);

David J. Pilling, Los Altos Hills, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 8/18 (2006.01);
U.S. Cl.
CPC ...
Abstract

An integrated circuit delay device includes a digital delay line configured to provide a percent-of-clock period delay to a timing signal received at an input thereof, in response to a control signal. This control signal has a value that specifies a length of the delay. A delay line control circuit is also provided. The delay line control circuit is configured to generate the control signal by counting multiple cycles of a high frequency oscillator signal (e.g., ring oscillator signal) having a period less than the clock period, over a time interval having a duration greater than the clock period.


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