The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 10, 2007
Filed:
Feb. 07, 2002
Yee-chia Yeo, Albany, CA (US);
Fu Liang Yang, Hsin-Chu, TW;
Chen Ming HU, Hsin-Chu, TW;
Taiwan Semiconductor Manufacturing Company , Ltd., Hsin-Chu, TW;
Abstract
An ultra thin MOSFET device structure located on an insulator layer, and a method of forming the ultra thin MOSFET device structure featuring a strained silicon channel located on the underlying insulator layer, has been developed. After epitaxial growth of a semiconductor alloy layer such as silicon-germanium (SiGe), on a first semiconductor substrate, a strained silicon channel layer, under biaxial tensile strain, is epitaxially grown on the underlying semiconductor alloy layer. Bonding of the strained silicon channel layer of the first semiconductor substrate, to a silicon oxide layer located on the surface of a second semiconductor substrate, is followed by a cleaving procedure performed at the interface of the strained silicon channel layer and the underlying semiconductor alloy layer, resulting in the desired configuration comprised of strained silicon channel layer-underlying insulator layer-second semiconductor substrate. The MOSFET device is then formed featuring the strained silicon channel layer, on the underlying silicon oxide layer, with enhanced carrier mobility realized as a result of the biaxial tensile strain of the silicon channel layer.