The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 03, 2007

Filed:

Oct. 18, 2001
Applicants:

William C. Terrell, Thousand Oaks, CA (US);

Tracy Edmonds, Camarillo, CA (US);

Wayland Joeng, Agoura Hills, CA (US);

Eric Russell Peterson, Camarillo, CA (US);

Jean Kodama, Cerritos, CA (US);

Harun Muliadi, Thousand Oaks, CA (US);

Norman Chan, Diamond Bar, CA (US);

Rexford Hill, San Diego, CA (US);

Michael Nishimura, San Diego, CA (US);

Stephen How, San Diego, CA (US);

Inventors:

William C. Terrell, Thousand Oaks, CA (US);

Tracy Edmonds, Camarillo, CA (US);

Wayland Joeng, Agoura Hills, CA (US);

Eric Russell Peterson, Camarillo, CA (US);

Jean Kodama, Cerritos, CA (US);

Harun Muliadi, Thousand Oaks, CA (US);

Norman Chan, Diamond Bar, CA (US);

Rexford Hill, San Diego, CA (US);

Michael Nishimura, San Diego, CA (US);

Stephen How, San Diego, CA (US);

Assignee:

Qlogic, Corp., Aliso Viejo, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04L 12/28 (2006.01);
U.S. Cl.
CPC ...
Abstract

A router for use in a network includes a scalable architecture and performs methods for implementing quality of service on a logical unit behind a network port; and for implementing storage virtualization. The architecture includes a managing processor, a supervising processor; and a plurality of routing processors coupled to a fabric. The managing processor has an in-band link to a routing processor. A routing processor receives a frame from the network, determines by parsing the frame, the protocol and logical unit number, and routes the frame to a queue according to a traffic class associated with the logical unit number in routing information prepared for the processors. An arbitration scheme empties the queue in accordance with a deficit round robin technique. If a routing processor detects the frame's destination is a virtual entity, and so is part of a virtual transaction, the router conducts a nonvirtual transaction in concert with the virtual transaction. The nonvirtual transaction accomplishes the intent of the virtual transaction but operates on an actual network port, for example, a storage device.

Published as:

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