The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 27, 2007
Filed:
Aug. 30, 2004
Erik Breiland, Colchester, VT (US);
Timothy W. Budell, Milton, VT (US);
Charles S. Chiu, Essex Junction, VT (US);
Paul L. Clouser, Williston, VT (US);
Charles K. Erdelyi, Essex Junction, VT (US);
Brian P. Welch, Scotia, NY (US);
Erik Breiland, Colchester, VT (US);
Timothy W. Budell, Milton, VT (US);
Charles S. Chiu, Essex Junction, VT (US);
Paul L. Clouser, Williston, VT (US);
Charles K. Erdelyi, Essex Junction, VT (US);
Brian P. Welch, Scotia, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
The invention relates generally to a method of power supply noise and signal integrity analysis for creating frequency-dependent electrical models particularly related to microelectronic packages. The method discloses creation of equivalent circuits for geometries encountered in a typical chip package, including how to partition the geometry into cells which are less then 1/20 the minimum wavelength (λ) in size, and how to handle signal and power supply vias, signal wires, and power planes. The method also instructs how to assign values to each of the inductors, capacitors, resistors, and transmission lines in each equivalent circuit. The method further provides modeling of only those interactions which occur between adjacent cells.