The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7196534 B1

PDF
Full Text
Expired
Date of Patent:
Mar. 27, 2007

Filed:

Dec. 18, 2003
Applicant:

Hideyuki Oshima, Tokyo, JP;

Inventor:

Hideyuki Oshima, Tokyo, JP;

Assignee:

Advantest Corp., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01); G06F 11/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

Output data of a device under test (DUT) is obtained at timing of both rising and falling edges of a clock output from the DUT, and output data of a DDR type device is fetched in synchronization with the clock. A semiconductor test apparatus comprises a clock side time interpolatorwhich obtains clocks input from a DUTby a plurality of strobes of constant timing intervals and which outputs the clocks as time-sequential level data, a data side time interpolatorwhich obtains output data input from the DUTby a plurality of strobes of constant timing intervals and which outputs the output data as time-sequential level data, and an edge selectorwhich switches the time-sequential level data obtained by the time interpolatorsand selectively outputs level data indicating rising and/or falling edges of the level data.


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