The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 27, 2007
Filed:
Oct. 15, 2004
Masakuni Shiozawa, Sakata, JP;
Masakuni Shiozawa, Sakata, JP;
Seiko Epson Corporation, Tokyo, JP;
Abstract
A method for manufacturing a semiconductor device includes, (a) mounting a plurality of first semiconductor chips in a manner not to overlap with one another on a substrate having a plurality of wiring patterns formed thereon, and electrically connecting each of the first semiconductor chips to any one of the wiring patterns, (b) conducting an electrical examination on a plurality of mounted bodies each including one of the first semiconductor chips and any one of the wiring patterns electrically connected to each other, (c) stacking a second semiconductor chip on the first semiconductor chip of any one of the mounted bodies that pass the electrical examination, excluding any of the mounted bodies that fail the electrical examination and thereafter, (d) cutting the substrate so as to divide the wiring patterns. The electrical examination in step (b) includes a test on each of the wiring patterns, a test on each of the first semiconductor chips, and a test on an electrical connection state between each of the first semiconductor chips and a corresponding one of the wiring patterns, and wherein the electrical examination is a success when passing all of the tests, and the electrical examination is a failure when failing at least one of the tests.