The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 20, 2007
Filed:
Feb. 04, 2005
Kyoung-woo Lee, Seoul, KR;
Hong-jae Shin, Seoul, KR;
Jae-hak Kim, Seoul, KR;
Young-jin Wee, Seongnam-si, KR;
Seung-jin Lee, Suwon-si, KR;
Ki-kwan Park, Haeundae-gu, KR;
Kyoung-Woo Lee, Seoul, KR;
Hong-Jae Shin, Seoul, KR;
Jae-Hak Kim, Seoul, KR;
Young-Jin Wee, Seongnam-si, KR;
Seung-Jin Lee, Suwon-si, KR;
Ki-Kwan Park, Haeundae-gu, KR;
Samsung Electronics Co., Ltd., Gyeonggi-do, KR;
Abstract
The present invention discloses a method of fabricating interconnection lines for a semiconductor device. The method includes forming an interlayer insulating layer on a semiconductor substrate. A via hole is formed through the interlayer insulating layer. A via filling material is formed to fill the via hole. A photoresist pattern is formed on the via filling material. The via filling material and the interlayer insulating layer are anisotropically etched using the photoresist pattern as an etch mask to form a trench. A residual portion of the via filling material is removed using two wet etch processes. After removing the residual portion of the via filling material, a conductive layer pattern is formed in the via hole and the trench.