The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 13, 2007
Filed:
May. 31, 2005
Zongwu Tang, Pleasanton, CA (US);
Juhwan Kim, Pleasanton, CA (US);
Daniel Zhang, San Jose, CA (US);
Haiqing Wei, San Jose, CA (US);
Gang Huang, San Jose, CA (US);
ZongWu Tang, Pleasanton, CA (US);
Juhwan Kim, Pleasanton, CA (US);
Daniel Zhang, San Jose, CA (US);
Haiqing Wei, San Jose, CA (US);
Gang Huang, San Jose, CA (US);
Synopsys, Inc., Mountain View, CA (US);
Abstract
A method for performing layout verification involves identifying feature centerlines in a mask layout, and then performing lithography simulation along the centerlines to generate a set of intensity distributions. At each local maxima or minima in the intensity distributions, further lithography simulation can be performed to determine an exposure pattern width at those local maxima/minima (check positions). The exposure pattern widths can then be evaluated to determine whether an actual pinch or bridge defect will be generated at those locations. If defect generation is likely (based on the lithographical simulation) at a particular location, the corresponding portion of the mask layout can be redesigned to avoid defect generation during actual production. In this method, accurate layout verification can be performed with a minimum of time-consuming lithography modeling.