The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7191414 B1

PDF
Full Text
Expired
Date of Patent:
Mar. 13, 2007

Filed:

Aug. 03, 2005
Applicant:

John F. Croix, Austin, TX (US);

Inventor:

John F. Croix, Austin, TX (US);

Assignee:

Nascentric, Inc., Austin, TX (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

In one embodiment, a system comprises a computer. The computer is configured to generate a plurality of partial sums corresponding to a first time point of a response on an interconnect, and generate the response at the first time point as a sum of the partial sums. The plurality of partial sums are a function of at least: one or more poles and residues of the interconnect and a time step; wherein at least a first partial sum of the plurality of partial sums is also a function of the first partial sum calculated for a second time point that precedes the first time point.


Find Patent Forward Citations

Croix, John. (2007). Apparatus and methods for interconnect simulation in electronic circuitry using non-uniform time step (U.S. Patent No. 7191414). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7191414

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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