Semiconductor storage device and method of selecting bit line of the semiconductor storage device

Abstract

Of bit line selection address bits A(k) to A(k+3), address bits A(k+1) and A(k+2) are subjected to exclusive OR operation with address bit A(k+3) by an address conversion circuitand when address bit A(k+3) is at high level, the address is inputted to an upper column decoderwith their logical levels inverted. In left and right areas AAand AAof eight bit lines within subarray AA, the order of selecting bit lines is switched in ascending order and descending order every four lines. With the construction of a lower pass gatethat alternately selects the left and right areas AAand AAfor each access, in continuous access within subarray and between subarrays, the distance between bit lines selected in adjacent accesses can be sufficiently secured, so that the electrical influence of a bit line accessed previously exerts no influence on a bit line accessed subsequently.