The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7190610 B1

PDF
Full Text
Expired
Date of Patent:
Mar. 13, 2007

Filed:

Aug. 31, 2005
Applicants:

John D. Porter, Meridian, ID (US);

William N. Thompson, Meridian, ID (US);

Inventors:

John D. Porter, Meridian, ID (US);

William N. Thompson, Meridian, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

An SRAM memory cell is provided having a pair of cross-coupled CMOS inverters. The sources of the pull-up transistors forming each of the CMOS inverters are coupled to Vthrough parasitic resistance of the substrate in which each is formed. The source of the p-type pull-up transistor is therefore always at a potential less than or equal to the potential of the N-well such that the emitter-base junction of the parasitic PNP transistor cannot become forward biased and latch-up cannot occur.


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Porter, John. (2007). Latch-up prevention for memory cells (U.S. Patent No. 7190610). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7190610

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