The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 13, 2007

Filed:

Dec. 04, 2003
Applicant:

Owais Jamil, San Jose, CA (US);

Inventor:

Owais Jamil, San Jose, CA (US);

Assignee:

Tessera, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01K 3/10 (2006.01);
U.S. Cl.
CPC ...
Abstract

A microelectronic element is formed from a structure including metal layers on top and bottom sides of a dielectric. Apertures are formed in the top metal layer, and vias are formed in the dielectric in alignment with the apertures. Top and bottom conductive features are formed in proximity to the vias, as by selectively depositing a metal on the metal layers or selectively etching the metal layers. The top and bottom conductive features are connected to one another by depositing a conductive material into the vias, most preferably without seeding the vias as, for example, by depositing solder in the vias.


Find Patent Forward Citations

Jamil, Owais. (2007). Method of making a microelectronic package (U.S. Patent No. 7188413). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7188413

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…