The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 06, 2007
Filed:
Apr. 11, 2003
Mark Steven Hahn, Milpitas, CA (US);
Mark Steven Hahn, Milpitas, CA (US);
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
A method for generating a model for a circuit having logic components is provided. The method includes identifying interface path logic components of the logic components so as to define shell logic, and identifying at least one of the logic components on which a constraint has been annotated so as to define constrained logic components. A subset of the logic components to preserve is then determined, the subset including the shell logic and the constrained logic components so as to define preserved logic. The model is then formed from the preserved logic. A highly accurate model can thus be created, while reducing computational and memory requirements. On-the-fly regeneration of the model is also possible, as is dominant path logic preservation.