The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 06, 2007
Filed:
Oct. 31, 2005
James William Adkisson, Jericho, VT (US);
Charles Thomas Black, White Plains, NY (US);
Alfred Grill, White Plains, NY (US);
Randy William Mann, Jericho, VT (US);
Deborah Ann Neumayer, Danbury, CT (US);
Wilbur David Pricer, Charlotte, VT (US);
Katherine Lynn Saenger, Ossining, NY (US);
Thomas Mccarroll Shaw, Peekskill, NY (US);
James William Adkisson, Jericho, VT (US);
Charles Thomas Black, White Plains, NY (US);
Alfred Grill, White Plains, NY (US);
Randy William Mann, Jericho, VT (US);
Deborah Ann Neumayer, Danbury, CT (US);
Wilbur David Pricer, Charlotte, VT (US);
Katherine Lynn Saenger, Ossining, NY (US);
Thomas McCarroll Shaw, Peekskill, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method of forming an integrated ferroelectric/CMOS structure which effectively separates incompatible high temperature deposition and annealing processes is provided. The method of the present invention includes separately forming a CMOS structure and a ferroelectric delivery wafer. These separate structures are then brought into contact with each and the ferroelectric film of the delivery wafer is bonded to the upper conductive electrode layer of the CMOS structure by using a low temperature anneal step. A portion of the delivery wafer is then removed providing an integrated FE/CMOS structure wherein the ferroelectric capacitor is formed on top of the CMOS structure. The capacitor is in contact with the transistor of the CMOS structure through all the wiring levels of the CMOS structure.