The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 27, 2007
Filed:
Feb. 19, 2004
Applicant:
Hsin-shih Wang, Fremont, CA (US);
Inventor:
Hsin-Shih Wang, Fremont, CA (US);
Assignee:
Faraday Technology Corp., Hsin-Chu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract
A method of fabricating an integrated circuit. The integrated circuit has a semiconductor body. The method includes forming a plurality of basic units with the same component characteristic on the semiconductor body, and forming at least a layout layer to program the basic units for building a clocked logic circuit and a non-clocked logic circuit without placing restrictions on positions of the clocked logic circuit and the non-clocked logic circuit on the semiconductor body.
Wang, Hsin-Shih. (2007). Method of fabricating and integrated circuit through utilizing metal layers to program randomly positioned basic units (U.S. Patent No. 7185307). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7185307
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile