The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 27, 2007
Filed:
Jun. 17, 2005
Yutaka Ito, Tokyo, JP;
Takeshi Hashimoto, Tokyo, JP;
Eiji Yamasaki, Tokyo, JP;
Shigeo Takeuchi, Tokyo, JP;
Masayuki Kaneda, Tokyo, JP;
Yutaka Ito, Tokyo, JP;
Takeshi Hashimoto, Tokyo, JP;
Eiji Yamasaki, Tokyo, JP;
Shigeo Takeuchi, Tokyo, JP;
Masayuki Kaneda, Tokyo, JP;
Elpida Memory, Inc., Tokyo, JP;
Abstract
A semiconductor memory device including an on-chip ECC circuit and having a data retention mode which includes, in the order of state transition, an encoding state EEST by an error correction circuit in which the error correction circuit carries out calculation of parity bits of data of the memory cells, a burst self-refresh state BSST in which the memory cells are self-refreshed in a burst with a period shorter than in ordinary self-refresh, a power-off state PFST in which an internal power supply circuit is partially turned off, a power-on state PNST in which the internal power supply circuit, partially turned off, is turned on, and a decoding state EDST by the error correction circuit in which the error correction circuit corrects errors of the memory cells. In case a command for exiting from the data retention mode in the encoding state, transition may be made to an idle state IST so that re-entry may be made from the decoding state EDST to the BSST.