The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 27, 2007

Filed:

Mar. 27, 2001
Applicants:

Kinji Saijo, Yamaguchi-ken, JP;

Shingji Ohsawa, Yamaguchi-ken, JP;

Hiroaki Okamoto, Yamaguchi-ken, JP;

Kazuo Yoshida, Yamaguchi-ken, JP;

Tadatomo Suga, Yamaguchi-ken, JP;

Inventors:

Kinji Saijo, Yamaguchi-ken, JP;

Shingji Ohsawa, Yamaguchi-ken, JP;

Hiroaki Okamoto, Yamaguchi-ken, JP;

Kazuo Yoshida, Yamaguchi-ken, JP;

Tadatomo Suga, Yamaguchi-ken, JP;

Assignees:

Toyo Kohan Co., Ltd., Tokyo, JP;

Other;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/44 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of efficiently and inexpensively fabricating a chip-size package having an electrode pitch expanded by forming a conductor wiring on the electrode forming surface side of a semiconductor chip, especially, a method for facilitating wiring and bump forming. A semiconductor device comprising a semi-conductor elements and conductor wirings formed on the semiconductor elements by etching wiring-forming metal foil; and a fabrication method for a semiconductor device comprising the steps of laminating wiring forming metal foil on the electrode forming surface side on the semiconductor, forming a resist wiring pattern on the metal foil, etching the metal foil, and slicing the device into individual elements.


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