The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7183122 B1

PDF
Full Text
Expired
Date of Patent:
Feb. 27, 2007

Filed:

May. 19, 2004
Applicants:

Michael Dibattista, Santa Clara, CA (US);

Richard H. Livengood, San Jose, CA (US);

Elizabeth B. Varner, Palo Alto, CA (US);

Randall C. White, Westborough, MA (US);

Inventors:

Michael DiBattista, Santa Clara, CA (US);

Richard H. Livengood, San Jose, CA (US);

Elizabeth B. Varner, Palo Alto, CA (US);

Randall C. White, Westborough, MA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 21/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

Nano-machining for circuit edits through the front side or backside of an integrated circuit may be performed using a scanning probe system. The system may create access holes with smaller dimensions and facilitate nano-machining endpoint detection in some embodiments.


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DiBattista, Michael. (2007). Physical nano-machining with a scanning probe system for integrated circuit modification (U.S. Patent No. 7183122). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7183122

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