The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7181590 B1

PDF
Full Text
Expired
Date of Patent:
Feb. 20, 2007

Filed:

Aug. 28, 2003
Applicants:

Sailesh Kottapalli, San Jose, CA (US);

Nadeem H. Firasta, Mt. View, CA (US);

Inventors:

Sailesh Kottapalli, San Jose, CA (US);

Nadeem H. Firasta, Mt. View, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/10 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method and system for allowing a multi-threaded processor to share pages across different threads in a pre-validated cache using a translation look-aside buffer is disclosed. The multi-threaded processor searches a translation look-aside buffer in an attempt to match a virtual memory address. If no matching valid virtual memory address is found, a new translation is retrieved and the translation look-aside buffer is searched for a matching physical memory address. If a matching physical memory address is found, the old translation is overwritten with a new translation. The multi-threaded processor may execute switch on event multi-threading or simultaneous multi-threading. If simultaneous multi-threading is executed, then access rights for each thread is associated with the translation.


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Kottapalli, Sailesh. (2007). Method for page sharing in a processor with multiple threads and pre-validated caches (U.S. Patent No. 7181590). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7181590

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