The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 20, 2007
Filed:
Apr. 02, 2004
Natarajan Mahadeva Iyer, Leuven, BE;
Steven Thijs, Willebroek, BE;
Vesselin K. Vassilev, Leuven, BE;
Tom Daenen, Leuven, BE;
Vincent DE Heyn, Braives, BE;
Natarajan Mahadeva Iyer, Leuven, BE;
Steven Thijs, Willebroek, BE;
Vesselin K. Vassilev, Leuven, BE;
Tom Daenen, Leuven, BE;
Vincent De Heyn, Braives, BE;
Abstract
A method and system for evaluating the current-voltage characteristics of devices where negative resistance behavior is observed. More particularly the present invention relates to a method and system for evaluating accurately the electrical overstress or ESD performance of semiconductor devices during the voltage transition region (positive to negative). The method comprises applying a signal comprising at least two amplitudes within the pulse. By suitably adjusting the amplitude of the first level, such that it is high enough to trigger the device-under-test, and subsequently applying one or more levels within the same signal while keeping the device-under-test in the on-state, the device IV characteristics can be comprehensively extracted, without being limited by the system loadline. The method may use a rectangular pulse testing set-up, also known as transmission line measurement set-up, with a single loadline characteristic to determine a portion or the complete ESD characteristic of the device-under test.