The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 20, 2007
Filed:
Dec. 15, 2004
Stella Matarrese, San Jose, CA (US);
Luca G. Fasoli, San Jose, CA (US);
Oron Michael, Campbell, CA (US);
Cuong Q. Trinh, Fremont, CA (US);
Stella Matarrese, San Jose, CA (US);
Luca G. Fasoli, San Jose, CA (US);
Oron Michael, Campbell, CA (US);
Cuong Q. Trinh, Fremont, CA (US);
STMicroelectronics, Inc., Carrollton, TX (US);
Abstract
A programmable system device includes an embedded FLASH memory module and an embedded programmable logic device (PLD) module. A sole embedded power supply voltage generator generates a plurality of voltages for use by the FLASH memory module and the PLD module during programming, reading and erasing operations. A switching network receives at least some of the generated voltages and selectively chooses among and between the received generated voltages for application to the FLASH memory module and the PLD module depending on whether that particular module is engaged in programming, reading or erasing operations. A load adjustment circuit controls operation of the sole power supply voltage generator based on whether the generated voltages are being used by the FLASH memory module or the PLD module to account for differences in loading between the FLASH memory module and the PLD module during programming, reading and erasing operations. A voltage trimming circuit controls operation of the sole embedded power supply voltage generator to make adjustments in voltage level for at least some of the generated voltages depending on whether those generated voltages are being used by the FLASH memory module or the PLD module during programming, reading and erasing operations.