The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 13, 2007
Filed:
May. 09, 2003
Baw-ching Perng, Hsin-Chu, TW;
Yih-shung Lin, Sanchung, TW;
Ming-ta Lei, Hsin Chu, TW;
Ai-sen Liu, Hsinchu, TW;
Chia-hui Lin, Hsin-Chu, TW;
Cheng-chung Lin, Taipei, TW;
Baw-Ching Perng, Hsin-Chu, TW;
Yih-Shung Lin, Sanchung, TW;
Ming-Ta Lei, Hsin Chu, TW;
Ai-Sen Liu, Hsinchu, TW;
Chia-Hui Lin, Hsin-Chu, TW;
Cheng-Chung Lin, Taipei, TW;
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Abstract
A method of forming pluralities of gate sidewall spacers each plurality comprising different associated gate sidewall spacer widths including providing a first plurality of gate structures; blanket depositing a first dielectric layer over the first plurality of gate structures; blanket depositing a second dielectric layer over the first dielectric layer; etching back through a thickness of the first and second dielectric layers; blanket depositing a first photoresist layer to cover the first plurality and patterning to selectively expose at least a second plurality of gate structures; isotropically etching the at least a second plurality of gate structures for a predetermined time period to selectively etch away a predetermined portion of the first dielectric layer; and, selectively etching away the second dielectric layer to leave gate structures comprising a plurality of associated sidewall spacer widths.