The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 06, 2007
Filed:
Sep. 22, 2004
Alexander Tetelbaum, Hayward, CA (US);
Benjamin Mbouombouo, San Jose, CA (US);
Alexander Tetelbaum, Hayward, CA (US);
Benjamin Mbouombouo, San Jose, CA (US);
LSI Logic Corporation, Milpitas, CA (US);
Abstract
A method and computer program are disclosed for floorplanning and cell placement of an integrated circuit architecture that include steps of: (a) receiving as input a design for an integrated circuit architecture that includes a plurality of modules and an internal I/O ring; (b) creating a floorplan to define an area for placing module cells for each module in the plurality of modules wherein for each module that overlaps the internal I/O ring, an area of intersection between the area defined for placing the module cells and an area bounded by a side of the internal I/O ring for which the area of intersection is least is a global minimum for the plurality of modules; and (c) generating as output the floorplan for the integrated circuit architecture.