The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7172981 B1

PDF
Full Text
Expired
Date of Patent:
Feb. 06, 2007

Filed:

Sep. 02, 2004
Applicant:

Yoshiaki Kobayashi, Hitachinaka, JP;

Inventor:

Yoshiaki Kobayashi, Hitachinaka, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 21/67 (2006.01);
U.S. Cl.
CPC ...
Abstract

A sealed type container accommodating a semiconductor substrate is positioned to a load port of a semiconductor manufacturing apparatus. The semiconductor substrate is taken out of the container. An ionizer is used for static-charge-eliminating the semiconductor substrates before and after process treatment in a transport area between the load port and a treatment section. The static-charge-eliminated semiconductor substrate is accommodated in the container positioned to the load port. Thus, it is possible to decrease foreign materials adhering to the semiconductor substrate and errors in handling the semiconductor substrate.


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Kobayashi, Yoshiaki. (2007). Semiconductor integrated circuit device manufacturing method including static charge elimination (U.S. Patent No. 7172981). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7172981

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