The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 30, 2007
Filed:
Aug. 28, 2003
Michel Zecri, Colomiers, FR;
Patrice Besse, Toulouse, FR;
Nicolas Nolhier, Toulouse, FR;
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
An arrangement () and method for scalable ESD protection of a semiconductor structure (), a protection structure () providing a discharge transistor () path from an input/output node () to ground or another node if a threshold voltage is reached, wherein the discharge transistor is a self-triggered transistor having collector/drain () and emitter/source () regions, and a base/bulk region () having one or more floating regions () between the collector/drain () and emitter/source () regions. The floating region (N or P) modulates the threshold voltage Vtl for ESD protection. Vtl can be adjusted by shifting the floating region location. Splitting of the electric field into two parts reduces the maximum of the electric field. Vtcan be adjusted volt-by-volt to suit application needs. ESD capability is increased by better current distribution in the silicon. This provides the advantages of reduced die size, faster time-to-market, less redesign cost, and better ESD performance.