The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 30, 2007
Filed:
Aug. 11, 2004
Shenqing Fang, Fremont, CA (US);
Kuo-tung Chang, Saratoga, CA (US);
Pavel Fastenko, Sunnyvale, CA (US);
Zhigang Wang, Sunnyvale, CA (US);
Shenqing Fang, Fremont, CA (US);
Kuo-Tung Chang, Saratoga, CA (US);
Pavel Fastenko, Sunnyvale, CA (US);
Zhigang Wang, Sunnyvale, CA (US);
Spansion LLC, Sunnyvale, CA (US);
Abstract
According to one exemplary embodiment, a method for fabricating a floating gate memory cell on substrate comprises a step of forming a spacer adjacent to a source sidewall of a stacked gate structure, where the stacked gate structure is situated over a channel region in substrate. The method further comprises forming a high energy implant doped region adjacent to the spacer in the source region of substrate. The method further comprises forming a recess in a source region of the substrate, where the recess has a sidewall, a bottom, and a depth, and where the sidewall of the recess is situated adjacent to a source of the floating gate memory cell. According to this exemplary embodiment, the spacer causes the source to have a reduced lateral straggle and diffusion in the channel region, which causes a reduction in drain induced barrier lowering (DIBL) in the floating gate memory cell.