The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 30, 2007
Filed:
Jul. 07, 2004
Chung Foong Tan, Singapore, SG;
Jinping Liu, Singapore, SG;
Hyeokjae Lee, Singapore, SG;
Kheng Chok Tee, Singapore, SG;
Elgin Quek, Singapore, SG;
Chung Foong Tan, Singapore, SG;
Jinping Liu, Singapore, SG;
Hyeokjae Lee, Singapore, SG;
Kheng Chok Tee, Singapore, SG;
Elgin Quek, Singapore, SG;
Chartered Semiconductor Manufacturing, Ltd, Singapore, SG;
Abstract
A structure and method for forming a carbon-containing layer in at least a portion of the end of range regions of implanted PAI and/or doped regions. The C-containing layer/region getters defects from the implanted PAI region or doped region. Example embodiments show a C-containing layer under at FET. Other example embodiments show an implanted C-containing regions implanted into the EOR region of implanted doped regions, such as pocket regions, S/D regions and SDE regions. Low temperature anneals can be used because the carbon-containing layer reduces defects.