The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 23, 2007

Filed:

Jul. 15, 2005
Applicants:

Pavel Poplevine, Foster City, CA (US);

Annie-li-keow Lum, Milpitas, CA (US);

Hengyang Lin, San Jose, CA (US);

Andrew J. Franklin, Santa Clara, CA (US);

Inventors:

Pavel Poplevine, Foster City, CA (US);

Annie-Li-Keow Lum, Milpitas, CA (US);

Hengyang Lin, San Jose, CA (US);

Andrew J. Franklin, Santa Clara, CA (US);

Assignee:

National Semiconductor Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 11/34 (2006.01); G11C 14/00 (2006.01); G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
Abstract

A non-volatile memory (NVM) cell splits its basic function, i.e. program, erase, read and control, among a four PMOS transistor structure, allowing independent optimization of each function. The cell structure also includes an embedded static random access memory (SRAM) cell that utilizes a latch structure to preprogram data to be written to the cell. The programming method for the cell utilizes a reverse Fowler-Nordheim tunneling mechanism with a very small programming current, allowing an entire NVM array to be programmed at one cycle.


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