Drain extended mos transistors with multiple capacitors and methods of fabrication

Abstract

Multi-capacitor drain extended transistor devices and methods are provided. A first capacitor structure comprises a first dielectric layer () and a first gate layer () and first and second lateral sides. The first capacitor structure overlies a channel region of a first conductivity type in a semiconductor substrate (). A second capacitor structure comprising a second dielectric layer () and a second gate layer () is formed overlying the first gate structure. A source region () of a second conductivity type formed in the semiconductor substrate () proximate the first lateral side of the gate and a drain extension region/well () lightly doped of the second conductivity type is formed in the semiconductor substrate under a portion of the gate structure. A drain region () of the second conductivity type formed within the drain extension region (). The first capacitor structure and the second capacitor structure connect in series to permit a higher operational gate voltage. Other systems and methods are disclosed.