The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 23, 2007
Filed:
Nov. 14, 2003
Abiola Awujoola, Union City, CA (US);
Clifford R. Fishley, San Jose, CA (US);
Abiola Awujoola, Union City, CA (US);
Clifford R. Fishley, San Jose, CA (US);
LSI Logic Corporation, Milpitas, CA (US);
Abstract
A carrier substrate includes an access region placed within the interior of the substrate that facilitates backside access to an integrated circuit die without damaging electrical integrity of the carrier substrate, a ring of die connection pads placed around the access region, and an array of package connection pads positioned around the perimeter of the top surface of the carrier substrate. In one embodiment, the perimeter depth of the array of package connections pads is selected to correspond to the number of electrical traces routable between minimally spaced package connection pads. The basic carrier substrate design is used to create an integrated circuit carrier family with each particular circuit carrier configured to receive a range of integrated circuit sizes and I/O counts such that each circuit carrier overlaps in size range with at least one other circuit carrier.