The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 16, 2007
Filed:
Jun. 07, 2005
Sushil Kumar Gupta, Noida, IN;
Paras Garg, Ghaziabad, IN;
Sushil Kumar Gupta, Noida, IN;
Paras Garg, Ghaziabad, IN;
STMicroelectronics PVT. Ltd., Noida, IN;
Abstract
The present invention provides a high-voltage tolerant input buffer circuit including a first NMOS transistor having its source terminal connected to the input pin, its gate terminal connected to a first reference voltage and its drain terminal connected to a first output terminal; a second NMOS transistor having its gate terminal connected to said first reference voltage and its source terminal connected to said first output terminal; a first PMOS transistor having its gate terminal connected to the drain terminal of said second NMOS transistor, its drain terminal connected to a second reference voltage lower than said first reference voltage and its source terminal connected to a second output terminal; a second PMOS transistor having its drain terminal connected to the drain terminal of said second NMOS transistor, its source terminal connected to said second output terminal, and its gate terminal connected to a control voltage; and a third PMOS transistor having its drain terminal connected to said second output terminal, its source terminal connected to a supply voltage, and its gate terminal connected to said control voltage.