The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 16, 2007
Filed:
Aug. 26, 2002
Wagdi W. Abadeer, Jericho, VT (US);
Jeffrey S. Brown, Middlesex, VT (US);
David M. Fried, Ithaca, NY (US);
Robert J. Gauthier, Jr., Hinesburg, VT (US);
Edward J. Nowak, Essex Junction, VT (US);
Jed H. Rankin, South Burlington, VT (US);
William R. Tonti, Essex Junction, VT (US);
Wagdi W. Abadeer, Jericho, VT (US);
Jeffrey S. Brown, Middlesex, VT (US);
David M. Fried, Ithaca, NY (US);
Robert J. Gauthier, Jr., Hinesburg, VT (US);
Edward J. Nowak, Essex Junction, VT (US);
Jed H. Rankin, South Burlington, VT (US);
William R. Tonti, Essex Junction, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
The present invention provides methods for fabrication of fin-type field effect transistors (FinFETs) and thick-body devices on the same chip using common masks and steps to achieve greater efficiency than prior methods. The reduction in the number of masks and steps is achieved by using common masks and steps with several scaling strategies. In one embodiment, the structure normally associated with a FinFET is created on the side of a thick silicon mesa, the bulk of which is doped to connect with a body contact on the opposite side of the mesa. The invention also includes FinFETs, thick-body devices, and chips fabricated by the methods.