The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 16, 2007
Filed:
Jan. 08, 2003
Hiroaki Kikuchi, Chitose, JP;
Toshiaki Sawada, Koganei, JP;
Hirohiko Yamamoto, Hachioji, JP;
Renesas Technology Corp., Tokyo, JP;
Hitachi ULSI Systems Co., Ltd., Tokyo, JP;
Renesas Northern Japan Semiconductor, Inc., Chitose, JP;
Abstract
Upon formation of an impurity-added silicon film by a low-pressure CVD apparatus, diffusion of an impurity from another similar silicon film, which has already been formed over the inside walls of the deposition chamber, is suppressed in the following manner. After insertion of a semiconductor substrate, having a gate oxide film (insulating film) formed thereover, into the deposition chamber of a CVD apparatus (first film forming apparatus), the inside of the deposition chamber is heated while minimizing, relative to a time A required for heating of the inside of the deposition chamber under atmospheric pressure, a time B required for the subsequent heating in the deposition chamber under a pressure adjusted to vacuum or not greater than atmospheric pressure. The formation of an impurity-added silicon film is then started. At this time, the relation between A and B is controlled to satisfy the following equation: 0.1×B≦A≦13×B.