The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7162707 B1

PDF
Full Text
Expired
Date of Patent:
Jan. 09, 2007

Filed:

May. 28, 2003
Applicants:

Toshihiro Kanaoka, Hyogo, JP;

Genichi Tanaka, Hyogo, JP;

Inventors:

Toshihiro Kanaoka, Hyogo, JP;

Genichi Tanaka, Hyogo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G01R 31/28 (2006.01);
U.S. Cl.
CPC ...
Abstract

An intra-area connection order determining unit determines at random orders of connection of scan path circuits in each area divided by an placement area dividing unit. An inter-area connection order determining unit determines orders of connection of the scan path circuits between the areas such that length of interconnection between the areas divided by the placement area dividing unit becomes short. Accordingly, length of interconnection between the scan paths can be locally made short, reducing congestion of interconnections and generation of hold time errors.


Find Patent Forward Citations

Kanaoka, Toshihiro. (2007). Scan path timing optimizing apparatus determining connection order of scan path circuits to realize optimum signal timings (U.S. Patent No. 7162707). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7162707

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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