Static random access memory device having a memory cell with multiple bit-elements

Abstract

A memory cell for a static random access memory (SRAM) is disclosed that can be programmed to have a one-bit cell or a multi-bit cell (i.e, including two or more latches) according to a desired amount of cell current. For lower current needs, the memory cell can incorporate a single bit-element, while for higher current needs the memory cell can incorporate two or more bit-elements. An exemplary static random access memory device includes a memory cell having one or more bit-elements, such as bistable latches. Access devices, such as pass transistors, are coupled between each of the bit-elements and a bit line. A word line is coupled to the control terminal of each of the pass transistors for controlling communication between the bit-elements and the bit line.