The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 09, 2007
Filed:
Nov. 12, 2002
Shubneesh Batra, Boise, ID (US);
Michael D. Chaine, Boise, ID (US);
Brent Keeth, Boise, ID (US);
Salman Akram, Boise, ID (US);
Troy A. Manning, Meridian, ID (US);
Brian Johnson, Boise, ID (US);
Chris G. Martin, Boise, ID (US);
Todd A. Merritt, Boise, ID (US);
Eric J. Smith, Boise, ID (US);
Shubneesh Batra, Boise, ID (US);
Michael D. Chaine, Boise, ID (US);
Brent Keeth, Boise, ID (US);
Salman Akram, Boise, ID (US);
Troy A. Manning, Meridian, ID (US);
Brian Johnson, Boise, ID (US);
Chris G. Martin, Boise, ID (US);
Todd A. Merritt, Boise, ID (US);
Eric J. Smith, Boise, ID (US);
Micron Technology, Inc., Boise, ID (US);
Abstract
A method of reducing parasitic capacitance in an integrated circuit having three or more metal levels is described. The method comprises forming a bond pad at least partially exposed at the top surface of the integrated circuit, forming a metal pad on the metal level below the bond pad and forming an underlying metal pad on each of the one or more lower metal levels. In the illustrated embodiments, the ratio of an area of at least one of the underlying metal pads to the area of the bond pad is less than 30%. Parasitic capacitance is thus greatly reduced and signal propagation speeds improved.