The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 02, 2007

Filed:

Mar. 29, 2005
Applicants:

Chen-chi Kuo, Pleasanton, CA (US);

Senthil Nathan Arunachalam, Sunnyvale, CA (US);

Sridhar Lakshmanamurthy, Sunnyvale, CA (US);

Uday Naik, Fremont, CA (US);

Inventors:

Chen-Chi Kuo, Pleasanton, CA (US);

Senthil Nathan Arunachalam, Sunnyvale, CA (US);

Sridhar Lakshmanamurthy, Sunnyvale, CA (US);

Uday Naik, Fremont, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 8/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

An arrangement of buffer in a memory unit including a plurality of memory banks may store information in rows that span the memory banks. Moreover, a processor may be adapted to (i) establish a plurality of buffers to be associated with the memory unit, wherein the size of each buffer is less than the width of a memory bank, and (ii) arrange for a selected buffer to begin in a memory bank other than a memory bank in which a previously selected buffer begins.


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