Semiconductor device with triple surface impurity layers

Abstract

An operational withstand voltage of a high voltage MOS transistor is enhanced and a variation in a saturation current Idsat is suppressed. A gate insulation film is formed on a P-type semiconductor substrate. A gate electrode is formed on the gate insulation film. A first low impurity concentration source layer and a first low impurity concentration drain layer are formed by tilt angle ion implantation of double charge phosphorus ions (P) using the gate electrode as a mask. Then a second low impurity concentration source layer and a second low impurity drain layer are formed by tilt angle ion implantation of single charge phosphorus ions (P). Furthermore, surface injection layers are formed by implanting arsenic ions (As) shallowly into the surface of the semiconductor substrate, in which the first low impurity concentration source layer, the first low impurity concentration drain layer, the second low impurity concentration source layer and the second low impurity concentration drain layer are already formed, so that the impurity concentration in an uppermost surface of the P-type semiconductor substrate is increased.